Theoretical and Natural Science

- The Open Access Proceedings Series for Conferences


Theoretical and Natural Science

Vol. 14, 30 November 2023


Open Access | Article

Verilog-based digital clock design methodology

Yilin Wang * 1
1 Xidian University

* Author to whom correspondence should be addressed.

Theoretical and Natural Science, Vol. 14, 102-107
Published 30 November 2023. © 2023 The Author(s). Published by EWA Publishing
This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Citation Yilin Wang. Verilog-based digital clock design methodology. TNS (2023) Vol. 14: 102-107. DOI: 10.54254/2753-8818/14/20240902.

Abstract

A digital electronic clock is a sophisticated instrument that employs digital circuits to render the time—hours, minutes, and seconds—in a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clock’s essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate time intervals; the counter, which keeps track of elapsed time; and the decoder, responsible for converting raw data into a format suitable for display. The clock’s tangible representation of time is vividly brought to life on a light-emitting diode (LED) display of the seven-segment digital tube. This setup magnificently showcases two-digit representations for hours, minutes, and seconds, streamlining the user’s experience. Rigorous simulation revealed that the system adeptly meets its operational mandate, functioning seamlessly as a digital clock and thereby aligning perfectly with the stipulated design criteria.

Keywords

Verilog HDL, Digital clock, Frequency Divider, Counter, Decoder

References

1. Li, W., Li, S., Zeng, Q., & Zhou, C. (2023). A Review of Design of Digital Clock Based on Verilog HDL. Highlights in Science, Engineering and Technology, 46, 289–297.

2. Zhongjian Gao, Maojin Wei, Ruige Zhang, & Lianzhou Rao. (2016). Design study of Verilog hdl digital clock circuit. Journal of Pingxiang University (3), 5.

3. Fan, H., Wang, S., Mao, N., & Dai, K. (2019). Development of Tibetan Multifunctional Digital Clock Based on FPGA. Journal of Physics: Conference Series, 1288(1), 012023.

4. Sau, S., Paul, R., Biswas, T., & Chakrabarti, A. (2012). A novel AES-256 implementation on FPGA using co-processor-based architecture. Proceedings of the International Conference on Advances in Computing, Communications, and Informatics - ICACCI ‘12.

5. Tian, W, & Xingzhong, X. (2018). Design of verilog-based encoder and decoder for scma system. Modern Electronics Technique.

6. Hao, L. (2008). Design of general frequency divider based on fpga using verilog hdl. Science Mosaic.

7. Ren Q, Liu Yi, & Wu Ji. (2015). Research on the advantages of parametric module library in Verilog design. Instrumentation Technology (7), 2.

8. McNamara, M. T. Y. IEEE Standard Verilog Hardware Description Language. The Institute of Electrical and Electronics Engineers (2001). IEEE Computer Society, Washington, DC, 1364-2001.

9. Tala, D. K. (2003). Verilog tutorial. WWW page. http://www. asic-world. com/verilog/veritut. html. (in English).

10. Palnitkar, S. (2003). Verilog HDL: A Guide to Digital Design and Synthesis (Bk/CD-ROM). Prentice-Hall, Inc.

Data Availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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Volume Title
Proceedings of the 3rd International Conference on Computing Innovation and Applied Physics
ISBN (Print)
978-1-83558-191-9
ISBN (Online)
978-1-83558-192-6
Published Date
30 November 2023
Series
Theoretical and Natural Science
ISSN (Print)
2753-8818
ISSN (Online)
2753-8826
DOI
10.54254/2753-8818/14/20240902
Copyright
30 November 2023
Open Access
This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

Copyright © 2023 EWA Publishing. Unless Otherwise Stated